A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories
نویسندگان
چکیده
A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-mm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33MHz in 8-LUT cascades at 122mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs). [DOI: 10.1143/JJAP.45.3295]
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